High-level Data-Layout Transformations for Energy Reduction in Direct Mapped Caches

In order to reduce power consumption in data dominated embedded applications, a multi-level memory hierarchy containing caches is often introduced in the implementation. The cache memory used in this hierarchy must have simple tag-comparison mechanisms and tag array overhead for reduced energy. However, such cache architecture, a direct mapped cache, potentially also causes energy overhead due to the extra misses because of the limited freedom of its mapping organisation. An effective way to reduce the miss overhead is to careful place the data in main memory. We use a memory data-layout scheme that interleaves signals in main memory such these are mapped in different lines without conflicting each other. This method is integrated with an array padding technique for finer-tunning of the resulting data layout. In order to know where to place the data, we have studied the nature of the conflict misses in detail and developed a model to predict these for every signal of interest of the application. We show that it is possible to significantly reduce the miss rate and come as close to the theoretical lowest rate using a real-life multimedia kernel. Our results indicate that by adapting the data layout it is possible to reach using a direct mapped cache the equivalent miss rate of a 4 way associative cache of the same capacity. Hereby avoiding the overhead in energy per access of the more costly 4-way associative cache.